View NHD-27-12864UCW3_8939909.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

nhd - 2.7 - 12864ucw3 oled display module nhd - newhaven display 2.7 - 2.7 diagonal size 12864 - 128 x 64 pixel resolution uc - model w - emitting color: white 3 - +3v power supply newhaven display international, inc. 2661 galvin ct. elgin il, 60124 ph: 847 - 844 - 8795 fax: 847 - 844 - 8796 www.newhavendisplay.com nhtech@newhavendisplay.com nhsales@newhavendisplay.com
[ 2 ] document revision history revision date description changed by 0 10/3/2012 initial product release ak 1 3/30/2015 electrical characteristics updated ak 2 5/9/16 viewing angles and temperature ranges updated sb functions and features ? 128 x 64 pixel resolution ? built - in ss d 13 2 5 controller ? parallel or serial mpu interface ? single, low voltage p ower s upply ? rohs compliant
1 2 3 4 5 6 a b c d b c d 1 2 3 4 5 6 mechanical drawing a [3] the drawing contained herein is the exclusive property of newhaven display internatonal, inc. and shall not be copied, reproduced, and/or disclosed in any format without permission. nhd-2.7-12864ucw3 03/30/15 date unit model: mm gen. tolerance 0.3mm rev descripton date detail "a" scale (5:1) 0.45 0.48 0.45 0.48 segm en t 127 ( column 128 ) co mm on 75 ( row 1 ) co mm on 13 ( row 63 ) segment 0 ( column 1 ) co mm on 74 ( row 2 ) co mm on 12 ( row 64 ) confidential
[ 4 ] interface description parallel interface: pin no. symbol external connection function description 1 v ss power supply ground 2 v dd power supply supply voltage for oled and logic . 3 nc - no connect 4 d/c mpu register select signal. d/c =0: command, d/c =1: data 5 r/w or /wr mpu 6800 - interface: read/write select signal, r/w=1: read r/w: =0: write 8080 - interface: active low write signal. 6 e or /rd mpu 6800 - interface: operation e nable signal. falling edge triggered. 8080 - interface: active low read signal. 7 - 1 4 db0 C db 7 mpu 8 - bit b i - directional data bus lines. 1 5 nc - no connect 1 6 /res mpu active low reset signal. 1 7 /cs mpu active low chip select signal. 18 nc - no connect 19 bs2 mpu mpu interface select signal. 20 bs1 mpu mpu interface select signal. serial interface: pin no. symbol external connection function description 1 v ss power supply ground 2 v dd power supply supply voltage for oled and logic. 3 nc - no connect 4 d/c mpu register select signal. d/c=0: command, d/c=1: data 5 - 6 vss power supply ground 7 sclk mpu serial clock signal. 8 sdin mpu serial data input signal. 9 nc - no connect 10 - 14 vss power supply ground 15 nc - no connect 16 /res mpu active low reset signal. 17 /cs mpu active low chip select signal. 18 nc - no connect 19 bs2 mpu mpu interface select signal. 20 bs1 mpu mpu interface select signal. mpu interface pin selections pin name 6800 parallel 8 - bit interface 8080 parallel 8 - bit interface serial interface bs2 1 1 0 bs1 0 1 0
[ 5 ] mpu interface pin assignment summery bus interface data/command interface control signals d7 d6 d5 d4 d3 d2 d1 d0 e r/w /cs d/c /res 8 - bit 6800 d[7:0] e r/w /cs d/c /res 8 - bit 8080 d[7:0] /rd /wr /cs d/c /res spi tie low nc sdin sclk tie low /cs d/c /res wiring diagram s
[ 6 ] electrical characteristics item symbol condition min. typ. max. unit operating temperature range t op absolute max - 40 - +85 ? c storage temperature range t st absolute max - 4 0 - +90 ? c supply voltage vdd - - 3.3 3.5 v supply current (logic) idd ta=25c, vdd= 3.3v - - 4 ma supply current (display) icc vdd=3.3 v, 50% on - 175 185 ma vdd=3.3 v, 100% on - 295 310 ma sleep mode current idd+icc sleep - - 2 10 a h level input vih - 0.8*vdd - vdd v l level input vil - vss - 0.2*vdd v h level output voh - 0.9*vdd - vdd v l level output vol - vss - 0.1 * vdd v optical characteristics item symbol condition min. typ. max. unit optimal viewing angles top ? y+ - 80 - ? bottom ? y - - 80 - ? left x - - 80 - ? right x+ - 80 - ? contrast ratio cr - 2000:1 - - - response time rise tr - - 10 - us fall tf - - 10 - us brightness - 50% checkerboard 60 80 - cd/m 2 lifetime - ta=25c, 50% checkerboard 2 0,000 - - hrs note : lifetime at typ ical temperature is based on accelerated high - temperature operation. lifetime is tested at average 50% pixels on and is rated as hours until half - brightness . the display off command can be used to extend the lifetime of the display. luminance of active pixels will degrade faster than inactive pixels. residual (burn - in) images may occur . t o avoid this, every pixel should be illuminated uniformly. controller information build - in ssd1325 controller. please download specification at http://www.newhavendisplay.com/app_notes/ssd1325.pdf
[ 7 ] table of commands instruction code description reset value d/c hex db7 db6 db5 db4 db3 db2 db1 db0 set column address 0 0 0 15 a[5:0] b[5:0] 0 * * 0 * * 0 a5 b5 1 a4 b4 0 a3 b3 1 a2 b2 0 a1 b1 1 a0 b0 set column start and end address a[5:0]: column start address. range: 0 - 63d b[5:0]: column end address. range: 0 - 63d 0 63d set row address 0 0 0 75 a[6 :0] b[6 :0] 0 * * 1 a6 b6 1 a5 b5 1 a4 b4 0 a3 b3 1 a2 b2 0 a1 b1 1 a0 b0 set row start and end address a[ 6 :0]: row start address. range: 0 - 79 d b[6 :0]: row end address. range: 0 - 79 d 0 79d set contrast control 0 0 81 a[6:0] 1 * 0 a6 0 a5 0 a4 0 a3 0 a2 0 a1 1 a0 double byte command to select 1 out of 128 contrast steps. contrast increases as the value increases. 0x40 set current range 0 84~86 1 0 0 0 0 1 x1 x0 0x84 = quarter current range 0x85 = half current range 0x86 = full current range 0x84 set remap 0 0 a0 a[6:0] 1 * 0 a6 1 * 0 a4 0 * 0 a2 0 a1 0 a0 a[0] = 0; disable column address remap a[0] = 1; enable column address remap a[1] = 0; disable nibble remap a[1] = 1; enable nibble remap a[2] = 0; horizontal address increment a[2] = 1; vertical address increment a[4] = 0; disable com remap a[4] = 1; enable com a[6] = 0; disable com split odd/even a[6] = 1; enable com split odd/even 0 0 0 0 0 set display start line 0 0 a1 a[6:0] 1 * 0 a6 1 a5 0 a4 0 a3 0 a2 0 a1 1 a0 set display ram display start line register from 0 - 79. 0 set display offset 0 0 a2 a[6:0] 1 * 0 a6 1 a5 0 a4 0 a3 0 a2 1 a1 0 a0 set vertical shift by com from 0~79 . 0 display mode 0 a4/a7 1 0 1 0 0 x2 x1 x0 0xa4 = normal display 0xa5 = entire display on, all pixels grayscale level 15 0xa6 = entire display off 0xa7 = inverse display 0xa4 set multiplex ratio 0 0 a8 a[6:0] 1 * 0 a6 1 a5 0 a4 1 a3 0 a2 0 a1 0 a0 set mux ratio to n+1 mux n=a[6:0]; from 16mux to 80mux (0 to 14 are invalid) 80 master configuration 0 0 ad a[1:0] 1 * 0 * 1 * 0 * 1 * 1 * 0 a1 1 a0 a[0] = 0; disable dc - dc converter a[0] = 1; enable dc - dc converter a[1] = 0; disable internal vcomh a[1] = 1; enable internal vcomh 1 1 set display on/ off 0 ae~af 1 0 1 0 x3 1 1 1 0xae = display off (sleep mode) 0xaf = display on aeh set vcomh voltage 0 0 be a[5:0] 1 * 0 * 1 a5 1 a4 1 a3 1 a2 1 a1 0 a0 sets the vcomh voltage level 000000 - 011111. a[5:0] = 1xxxxx = 1.0*vref 010001
[ 8 ] set precharge voltage 0 0 bc a[7:0] 1 a7 0 a6 1 a5 1 a4 1 a3 1 a2 0 a1 0 a0 sets the precharge voltage level 00000000 - 00011111 a[7:0] = 1xxxxxxx connects to vcomh a[7:0] = 001xxxxx equals 1.0*vref 00011000 set phase length 0 0 0 b1 a[3:0] a[7:4] 1 * a7 0 * a6 1 * a5 1 * a4 0 a3 * 0 a2 * 0 a1 * 1 a0 * a[ 3:0] = p1. phase 1 period of 1 - 15 dclk clocks a[7:4] = p2. phase 2 period of 1 - 15 dclk clocks 3 5 set row period 0 0 b2 a[7:0] 1 a7 0 a6 1 a5 1 a4 0 a3 0 a2 1 a1 0 a0 sets number of dclks (k) per row. range 2 - 158dclks. k = p1 + p2 + gs15 pulse width (reset values: 3 + 5 + 29) 37dclks (0x25) set display clock divide ratio / oscillator frequency 0 0 0 b3 a[3:0] a[7:4] 1 * a7 0 * a6 1 * a5 1 * a4 0 a3 * 0 a2 * 1 a1 * 1 a0 * a[3:0] = define the divide ratio of the display clocks. range 1 - 16 divide ratio = a[3:0] +1 a[7:4] = set the oscillator frequency. frequency increases with the value of a[7:4]. range 0000b~1111b. 2 0 set grayscale table 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b8 a[2:0] b[2:0] b[6:4] c[2:0] c[6:4] d[2:0] d[6:4] e[2:0] e[6:4] f[2:0] f[6:4] g[2:0] g[6:4] h[2:0] h[6:4] 1 * * * * * * * * * * * * * * * 0 * * b6 * c6 * d6 * e6 * f6 * g6 * h6 0 * * b5 * c5 * d5 * e5 * f5 * g5 * h5 0 * * b4 * c4 * d4 * e4 * f4 * g4 * h4 1 * * * * * * * * * * * * * * * 0 a2 b2 * c2 * d2 * e2 * f2 * g2 * h2 * 0 a1 b1 * c1 * d1 * e1 * f1 * g1 * h1 * 0 a0 b0 * c0 * d0 * e0 * f0 * g0 * h0 * sets the gray scale level. range 1 - 15 a[2:0] = l1 b[2:0] = l2 b[6:4] = l3 c[2:0] = l4 c[6:4] = l5 d[2:0] = l6 d[6:4] = l7 e[2:0] = l8 e[6:4] = l9 f[2:0] = l10 f[6:4] = l11 g[2:0] = l12 g[6:4] = l13 h[2:0] = l14 h[6:4] = l15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 set biasing current for dc - dc converter 0 0 cf a[7:6] 1 a7 1 a6 0 * 0 * 1 * 1 * 1 * 1 * 0xf0 = high 0x70 = low 0xf0 nop 0 e3 1 1 1 0 0 0 1 1 command for no operation for detailed instruction information, see datasheet: http://www.newhavendisplay.com/app_notes/ssd1325.pdf
[ 9 ] mpu interface for detailed timing information, see datasheet: http://www.newhavendisplay.com/app_notes/ssd1325.pdf 6800 - mpu parallel interface the parallel interface consists of 8 bi - directional data pins, r/w, d/c, e, and /cs. a low on r/w indicates write operation, and high on r/w indicate s read operation. a low on d/c indicates command read or write, and high on d/c indicates data read or write. the e input serves as data latch signal, while /c s is low. data is latched at the falling edge of e signal. function e r/w /cs d/c write command 0 0 0 read status 1 0 0 write data 0 0 1 read data 1 0 1 8080 - mpu parallel interface the parallel interface consists of 8 bi - directional data pins, /rd, /wr, d/c, and /cs. a low on d/c indicates command read or write, and high on d/c indicates data read or write. a rising edge of /rs input serves as a data read latch signal while /cs is low. a rising edge of /wr input serves as a data/comman d write latch signal while /cs is low. function /rd /wr /cs d/c write command 1 0 0 read status 1 0 0 write data 1 0 1 read data 1 0 1 alternatively, /rd and /wr can be kept stable while /cs serves as the data/command latch signal. function /rd /wr /cs d/c write command 1 0 0 read status 0 1 0 write data 1 0 1 read data 0 1 1
[ 10 ] seri al interface the serial interface consists of serial clock sclk, serial data sdin, d/c, and /cs. d0 acts as sclk and d1 acts as sdin. d2 should be left open. d3~d7, e, and r/w should be connected to gnd. function /rd /wr /cs d/c d0 write command 0 0 0 0 write data 0 0 0 1 sdin is shifted into an 8 - bit shift register on every rising edge of sclk in the order of d7, d6,d0. d/c is sampled on every eighth clock and the data byte in the shift register is written to the gdram or command register in the same clock. note: read is not available in serial mode. for detailed protocol information, see datasheet: http://www.newhavendisplay.com/app_notes/ssd1325.pdf
[ 11 ] example initialization sequence: set_display_on_off_12864(0x00); // display off (0x00/0x01) set_display_clock_12864(0x91); // set clock as 135 frames/sec set_multiplex_ratio_12864(0x3f); // 1/64 duty (0x0f~0x5f) set_display_offset_12864(0x4c); // shift mapping ram counter (0x00~0x5f) set_start_line_12864(0x00); // set mapping ram display start line (0x00~0x5f) set_master_config_12864(0x00); // disable embedded dc/dc converter (0x00/0x01) set_remap_format_12864(0x50); // set column address 0 mapped to seg0 // disable nibble remap // horizontal address increment // scan from com[n - 1] to com0 // en able com split odd even set_current_range_12864(0x02); // set full current range set_gray_scale_table_12864(); // set pulse width for gray scale table set_contrast_current_12864(brightness); // set scale factor of segment output current control s et_frame_frequency_12864(0x51); // set frame frequency set_phase_length_12864(0x55); // set phase 1 as 5 clocks & phase 2 as 5 clocks set_precharge_voltage_12864(0x10); // set pre - charge voltage level set_precharge_compensation_12864(0x20,0x02); / / set pre - charge compensation set_vcomh_12864(0x1c); // set high voltage level of com pin set_vsl_12864(0x0d); // set low voltage level of seg pin set_display_mode_12864(0x00); // normal display mode (0x00/0x01/0x02/0x03) fill_ram_12864(0x00); // clear screen set_display_on_off_12864(0x01); // display on (0x00/0x01)
[ 12 ] quality information test item content of test test condition note high temperature storage test the e ndurance of the display at high storage temperature . + 9 0 ? c , 240 hrs 2 low temperature storage test the e ndurance of the display at low sto rage temperature . - 4 0 ? c , 240 hrs 1,2 high temperature operation test the e ndurance of the display by applying electric stress (voltage & current) a t high t emperature. + 85 ? c 240h rs 2 low temperature operation test the e ndurance of the display by applying electric stress (voltage & current) a t low t emperature . - 4 0 ? c , 240 hrs 1 ,2 high temperature / humidity operation test the e ndurance of the display by applying electric stress (voltage & current) a t high t emperature with high humidity. + 6 0 ? c , 90% rh , 240 hrs 1,2 thermal shock resistance test the e ndurance of the display by applying electric stress (voltage & current) during a cycle of low and high t emperatures . - 40 ? c , 30min - > 25?c,5min - > 8 5 ? c,30min = 1 cycle 10 0 cycles vibration test test the e ndurance of the display by a pplying vibration to simulate transportation and use. 10 - 22 hz , 15mm amplitude. 22 - 500hz, 1.5g 30min in each of 3 directions x,y,z 3 atmospheric pressure test test the endurance of the display by applying atmospheric pressure to simulate transportation by air. 115mbar, 40hrs 3 static electricity test test the endurance of the display by applying electric static discharge. vs=800v, rs=1.5k , cs=100 pf one time note 1: no condensation to be observed. note 2: conducted after 2 hours of storage at 25 ? c, 0%rh. note 3: test performed on product itself, not inside a container . evaluation criteria: 1: display is fully functional during operational tests and after all tests, at room temperature. 2: no observable defects. 3: luminance >50% of initial value. 4: current consumption within 50% of initial value precautions for using oleds/ lcds/lcms see precautions at www.newhavendisplay.com/specs/precautions.pdf warranty information and terms & conditions http://www.newhavendisplay.com/index.php?main_page=terms

▲Up To Search▲

Price & Availability of NHD-27-12864UCW3

	To Download NHD-27-12864UCW3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .